DK-DEV-5SGXEA7N【PDF 185/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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SV51007

2014.01.10

Assignment name

Value

Field

Source-Synchronous Timing Budget

Assignment

Input Termination

Differential

6-29

Source-Synchronous Timing Budget

The topics in this section describe the timing budget, waveforms, and specifications for source-synchronous

signaling in the Stratix V device family.

The LVDS I/O standard enables high-speed transmission of data, resulting in better overall system

performance. To take advantage of fast system performance, you must analyze the timing for these high-

speed signals. Timing analysis for the differential block is different from traditional synchronous timing

analysis techniques.

The basis of the source synchronous timing analysis is the skew between the data and the clock signals instead

of the clock-to-output setup times. High-speed differential data transmission requires the use of timing

parameters provided by IC vendors and is strongly influenced by board skew, cable skew, and clock jitter.

This section defines the source-synchronous differential data orientation timing parameters, the timing

budget definitions for the Stratix V device family, and how to use these timing parameters to determine the

maximum performance of a design.

Differential Data Orientation

There is a set relationship between an external clock and the incoming data. For operations at 1 Gbps and

a serialization factor of 10, the external clock is multiplied by 10. You can set phase-alignment in the PLL

to coincide with the sampling window of each data bit. The data is sampled on the falling edge of the multiplied

clock.

Figure 6-28: Bit Orientation in the Quartus II Software

This figure shows the data bit orientation of the x10 mode.

incloc k/outcloc k

MSB

10 LVDS Bits

LSB

data in

9

8

7

6

5

4

3

2

1

0

Differential I/O Bit Position

Data synchronization is necessary for successful data transmission at high frequencies.

The following figure shows the data bit orientation for a channel operation and is based on the following

conditions:

? The serialization factor is equal to the clock multiplication factor.

? The phase alignment uses edge alignment.

? The operation is implemented in hard SERDES.

High-Speed Differential I/O Interfaces and DPA in Stratix V Devices

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